High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere |
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Authors: | Sano N Sekiya M Hara M Kohno A Sameshima T |
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Affiliation: | Res. Center, Sony Corp., Yokohama; |
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Abstract: | A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO 2 films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO2 and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H2O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×1010 cm-2 eV-1, and the effective oxide charge density from 1×10 12 to 5×109 cm-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm2 V-1 s-1 and the threshold voltage decreased from -5.5 to -1.7 V |
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