A high-performance thin-film transistor with a vertical offsetstructure

In this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (μc-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT). This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFTs with a much higher drivability. The fabrication process is simple, low temperature (⩽300°C), and low cost, with a potential for high reliability