基于FPGA的单稳态脉冲展宽电路的设计与实现

在数字电路中,经常需要对脉冲信号进行展宽或者压缩,以便后续处理.传统的方法是采用分立元件搭建的单稳态电路实现,针对这种电路的精度和稳定性易受外部环境的影响而变化,不适合在高精度和复杂环境下使用的状况,通过对用可编程逻辑器件FPGA实现单稳态脉冲展宽电路的功能进行研究,设计出三种基于FPGA的单稳态脉冲展宽电路,并进行了电路的仿真和测试比较,结果表明采用时钟计数方法实现的单稳态脉冲展宽电路不仅能有效、方便地对输入脉冲进行展宽和压缩,而且还极大地提高了电路的可靠性和脉冲处理的精度.

The designing and implementation of monostable pulse-expanding circuit based on FPGA device

In the digital circuit, expanding or compressing pulse signals is regular in order to predigest the disposal. The traditional way has the disposal to be implemented by monostable circuit composed from schism components, but the precision and the stability of the circuit are easily variational to the influence of outer environment, which is unsuitable to apply on high precious and steady occasions. To solve this problem, the function of implementing the monostable pluse-expanding circuit based on the FPGA device is proposed in this paper. We have designed three processes for constructing the monostable pluse-expanding circuit based on FPGA device and the characteristics of the circuit. We have also compared them with test and simulation. The results show that the monostable pulse-expanding circuits based on FPGA device not only effectively expand or compress the inputing pulse, but also greatly improve the stability and the precision of pluse-expanding circuits.