| 一种C波段小步进捷变频频率综合器的设计 |
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| 引用本文： | 由法宝,张春荣,余铁军.一种C波段小步进捷变频频率综合器的设计[J].火控雷达技术,2012(2):59-62. |
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| 作者姓名： | 由法宝 张春荣 余铁军 |
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| 作者单位： | 西安电子工程研究所,西安,710100 |
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| 摘 要： | 本文介绍了一种小步进、低相噪、低杂散、捷变频锁相频率综合器的设计与实现，本设计选用超低相噪锁相环芯片，采用小数分频实现小步进，通过双锁相环“乒乓”工作实现捷变频，经过对环路参数的精心设计，较好的实现了相位噪声、杂散等技术指标。
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| 关 键 词： | 小步进 低相噪 低杂散 捷变频 锁相频率综合器 |
Design of A C-band Small Step Agile Frequency Synthesizer |
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| You Fabao,Zhang Chunrong,Yu Tiejun.Design of A C-band Small Step Agile Frequency Synthesizer[J].Fire Control Radar Technology,2012(2):59-62. |
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| Authors: | You Fabao Zhang Chunrong Yu Tiejun |
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| Affiliation: | ( Xi＇an Electronic Engineering Resarch Institute, Xi＇an 7101 00 ) |
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| Abstract: | Development and implementation of a small step, low phase noise, low spur, agile PLL frequency syn-thesizer are presented. Ultralow phase noise PLL chip is selected in the design, using decimal frequency divider to implement small step, and using ping-pang operation of double PLLs to realize frequency agile. The technical spec-ifications like phase noise, spurious are better achieved by carefully designing loop parameters. |
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| Keywords: | small step low phase noise low spurious frequency agile PLL frequency synthesizer |
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