| 一种高速高线性采保电路的设计 |
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| 引用本文： | 周杨,张正瑶,李儒章. 一种高速高线性采保电路的设计[J]. 数字技术与应用, 2010, 0(12): 48-50 |
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| 作者姓名： | 周杨 张正瑶 李儒章 |
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| 作者单位： | [1]重庆邮电大学,重庆400065 [2]模拟集成电路国家级重点实验室,重庆400060 [3]中国电子科技集团公司第二十四研究所,重庆400060 |
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| 摘 要： | 本文设计了一种拓扑结构为开环,基于栅压自举开关技术的S/H电路。在Cadence Spectre环境下进行仿真,在1.6GSPS的采样速率下,当输入信号为775MHz,1Vpp的正弦波时,该采样/保持电路的SFDR达到55.63dB,THD为-53.93dB。
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| 关 键 词： | ad转换器 采样保持电路 高速 栅压自举 |
A new design of A High-Speed Highly-Linear CMOS S/H Circuit |
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| ZHOU Yang,ZHANG Zhengfan,LI Ruzhang. A new design of A High-Speed Highly-Linear CMOS S/H Circuit[J]. Digital Technology & Application, 2010, 0(12): 48-50 |
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| Authors: | ZHOU Yang ZHANG Zhengfan LI Ruzhang |
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| Affiliation: | 1.Chongqing University of Posts and Telecommunications, Chongqing 400065; 2.National Laboratory of Analog ICs, Chongqing 400060; 3.Sichuan Institute of Solid State Circuits, China Electronics Technology Group Corp.Chongqing 400060) |
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| Abstract: | This paper describes the high-speed and highly linear CMOS sample/hold circuit that was used in front end of an ADC.The archi tecture of sample/hold based on an open-loop structure that enables it operates in high speed.The sample/hold consists of highly linear openloop buffer and bootstrapped switch. Simulate with Cadence Spectre,this sample-and-hold circuit achieves 55.63dB SFDR,--53.93dB THD |
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| Keywords: | ad converter S/H high speed bootstrap switch |
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