Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.