Reliability evaluation of BOAC and normal pad stacked-chip packaging using low-K wafers

This work evaluates the wire bondability and the reliability tests for the stacked-chip TFBGA wire bond packaging with the Sn–4.0Ag–0.5Cu lead-free solder ball. The bonding-over-active-circuit (BOAC) pad is the top test chip and the normal pad is the bottom test chip and is combined in the stacked-chip packaging. Both test chips are 90 nm low-K dielectric with five copper layers and one layer aluminum pad and a background ranging from 775 μm to 150 μm. According to the simulation results, the maximum normal stress of low-K layer for the BOAC pad is higher than that of the normal pad by 146.4%. However, the maximum shear stress of Cu metal layer for the BOAC pad is lower than that of the normal pad by 64.2%. To compare the bonding pad strength for the BOAC and normal pad low-K wafers, this work uses the simplified two-layer model to extract the effective mechanical properties of the two bonding pad structures. The effective average Young’s modulus of the normal pad and the BOAC pad are 86 GPa and 69 GPa, respectively. The test results indicate that the effective Young’s modulus of the normal pad exceeds that of the BOAC pad by 17 GPa. The wire bondability test of the ball shear and the wire pull test results are superior to the specification by 80% and 83.75%, respectively. All stacked-chip TFBGA packaging samples underwent reliability tests, including HAST, TCT, and HTST. All the wire bondability and reliability tests passed the specification for the BOAC pad and the normal pad low-K structures. Accordingly, this work shows that the proposed stacked-chip TFBGA packaging passes the wire bondability and the reliability tests. The proposed packaging improves the electrical performance, enhances the utility of the active chip area and saves chip area through the use of low-K and BOAC chips. Furthermore, the results show that the equivalent stiffness of the bonding pad structure can be used as the bondability and reliability test index for the chip.