总线监视器的设计

随着集成电路设计规模的不断增加，传统的验证方法学由于无法提供足够的能力来检查系统所有可能功能的正确性，已经不能满足SoC验证的需求。验证重用方法学是解决这一问题的有效途径。在SoC的验证过程中．利用总线监视器对片上总线上发生的事务进行实时监视，并将监视结果以机器可读的格式显示出来，从而可以帮助验证工程师有效地判断数据传输的正确性，达到验证单个模块和系统功能的目的。本文提出了一种SoC功能。验证平台中总线监视器的设计方法，并给出了具体的实现过程。

The Design of a Bus Monitor

As the grows of the VLSI design scale, traditional verification methods can not satisfy the SoC verification request, because it dose not supply the enough ability to check all the function rightness and can not ensure the product quality. Verification reuse methodology can solve this problem effective. In SoC verification, we can make use of bus protocol checker to monitor bus, and monitored result display in a special format, so we can estimate the validity of bus data, and check models and the system. This paper advances the design method of bus monitor in SoC and presents the material implementation.