| 一种用于光通信的新型时钟提取电路设计 |
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| 引用本文： | 尹法纪,沈雷,马琪,陈科明. 一种用于光通信的新型时钟提取电路设计[J]. 光通信技术, 2009, 33(9) |
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| 作者姓名： | 尹法纪 沈雷 马琪 陈科明 |
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| 作者单位： | 1. 杭州电子科技大学微电子CAD研究所,杭州,310018
2. 杭州电子科技大学通信工程学院,杭州,310018 |
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| 基金项目： | 浙江省重大科技专项重点项目 |
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| 摘 要： | 提出了一种采用数据转换跟踪环的时钟提取电路设计方法,介绍了这种新环路的设计结构及工作原理,并对环路性能进行了理论分析和仿真.分析和仿真表明,该电路具有很好的跟踪性能,信噪比较低时可以保持锁定状态,有突发相位抖动出现时可快速进入锁定.可以用于光纤通信系统中.
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| 关 键 词： | 锁相环 数据转换跟踪环 时钟提取 |
A novel design approach of clock recovery circuit used in optical communication |
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| YIN Fa-ji,SHEN Lei,MA Qi,CHEN Ke-ming. A novel design approach of clock recovery circuit used in optical communication[J]. Optical Communication Technology, 2009, 33(9) |
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| Authors: | YIN Fa-ji SHEN Lei MA Qi CHEN Ke-ming |
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| Affiliation: | YIN Fa-ji1,SHEN Lei2,MA Qi1,CHEN Ke-ming1(1.Microelectronic CAD Center Hangzhou Dianzi University,Hangzhou 310018,China,2.School of Communication Engineering,Hangzhou Dianzi University,China) |
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| Abstract: | This paper proposes a novel design approach of clock recovery circuit using data transition tracking loop.It introduces the implementation structure and operation principle of the loop,and analyzes its perfor-mance.The simulation results show that the loop can keep locking when the SNR is low and can track quickly after gusty phase jitter occurs.It can be used in optical communication. |
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| Keywords: | PLL DTTL Clock Recovery |
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