A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip |
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| Authors: | Carlough SR Philhower RA Maier CA Steidl SA Campbell PM Garg A Kyung-Suc Nah Ernest MW Loy JR Krawczyk TW Jr Curran PF Kraft RP Greub HJ McDonald JF |
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| Affiliation: | Rensselaer Polytech. Inst., Troy, NY; |
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| Abstract: | A byte-slice datapath for exploring multi-chip RISC processor development in AlGaAs-GaAs heterojunction bipolar transistor (HBT) technology has been designed, fabricated and tested. The circuits are implemented using differential current-mode logic (CML) and emitter-coupled logic (ECL) with signal swings of 250 mV. Each datapath chip contains a single slice, including an 8-bit by 32-word single-port register file with a 230-ps read access time, and an 8-bit carry-select adder with a 140-ps select path and a 380-ps ripple-carry path. Each unpackaged die was tested using an at-speed boundary scan test scheme. The register file and adder carry chain are also implemented in a special test chip for accurate performance characterization of these critical circuits |
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