高速突发模式误码测试仪的FPGA实现方案

突发模式误码测试仪与一般连续误码测试仪不同,其接收端在误码比对前要实现在十几位内,对具有相位跳变特点的信号进行时钟提取和数据恢复,并且在误码比对时须滤除前导码和定界符,仅对有效数据进行误码统计。本文提出一种基于FPGA实现的高速突发模式误码测试仪设计方案,并介绍该方案的总体设计过程,以及FPGA中主要功能逻辑模块的工作原理和控制系统的设计。该测试仪应用于1.25GHz GPON系统突发式光接收模块的误码测试中,具有较好的性能和实际意义。

High-speed Burst-mode BER Tester Based on FPGA

Being different from general continual-data stream BER tester,the receiver of burst-mode BER tester is required to extract clock and recover data accurately from the incoming data steam characterized by phase variation within a dozen bits before error bits detection is conducted;moreover,during error bits detection,the receiver must filter the preamble and delimiter and gets error bits statistic only for payload.In this paper,a design method for burst-mode BER tester based on FPGA is put forward.The whole s...