Reducing average and peak temperatures of VLSI CMOS circuits by means of evolutionary algorithm applied to high level synthesis

In this paper an adaptive evolutionary algorithm (AEA) for high-level synthesis, resulting in reduction of the power dissipation in CMOS circuits is presented. It enables us to design contemporary electronic circuits/systems with minimisation of the peak and average power consumption, which leads to reduction of the peak and average temperature of the designed chip. Therefore, the reliability of the integrated circuit (IC) can be improved. The results of experiments carried out for the chosen benchmark circuits show that the achieved reduction of power consumption varies from 4 to 52%.