| 基于NiosII的SDH性能告警处理平台及实现 |
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| 引用本文： | 王江艳,唐宁,王小港. 基于NiosII的SDH性能告警处理平台及实现[J]. 中国集成电路, 2009, 18(7): 25-27 |
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| 作者姓名： | 王江艳 唐宁 王小港 |
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| 作者单位： | 上海贝尔股份有限公司公共能力中心,上海,201206 |
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| 摘 要： | 针对系统对于SDH性能告警处理方面的需求，利用Altera低成本的FPGA开发设计了基于NiosII嵌入式CPU的处理平台，利用SOPC Builder创建了NiosIISoC硬件系统，开发了嵌入式软件，从而实现对外围ASIC芯片的配置和性能告警处理算法。
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| 关 键 词： | SDH FPGA NiosII |
Design and Implementation of SDH Performance Alarm Platform Based on NiosII |
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| WANG Jiang-yan,TANG Ning,WANG Xiao-gang. Design and Implementation of SDH Performance Alarm Platform Based on NiosII[J]. China Integrated Circuit, 2009, 18(7): 25-27 |
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| Authors: | WANG Jiang-yan TANG Ning WANG Xiao-gang |
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| Affiliation: | (Common Competence Center, Alcatel-Lucent Shanghai Bell Co., Ltd. shanghai 201206,China) |
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| Abstract: | by using low configuration software. To meet the cost Ahera of external requirement of SDH performance alarm processing, a platform based on NiosII was designed FPGA. ASICs The hardware system of NiosII SoC was created by using SOPC Builder. The and the processing of performance alarm were implemented in NiosII Embedded |
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| Keywords: | SDH FPGA NiosII |
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