| 由锁相器提供时钟信号的晶闸管触发方案 |
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| 引用本文： | 刘铮,赵言涛,彭永进. 由锁相器提供时钟信号的晶闸管触发方案[J]. 电力电子技术, 2007, 41(1): 125-126 |
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| 作者姓名： | 刘铮 赵言涛 彭永进 |
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| 作者单位： | 湖南大学,湖南,长沙,410082;湖南大学,湖南,长沙,410082;湖南大学,湖南,长沙,410082 |
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| 摘 要： | 为了保持晶闸管的触发脉冲与主回路电源电压间严格的相位关系,提出了一种采用锁相环作为时钟信号源的基于可编程逻辑器(Complex Programmable Logic Device,简称CPLD)的晶闸管触发脉冲发生方案,可消除因量化引起的三相触发脉冲的不对称性并简化CPLD的编程.实验结果证明该触发方案可靠实用.
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| 关 键 词： | 晶闸管 触发 锁相环 |
| 文章编号： | 1000-100X（2007）01-0125-02 |
| 修稿时间： | 2006-07-04 |
Voltage Synchronous Triggering Scheme Clocked by Phase-Locked Loop |
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| LIU Zheng,ZHAO Yan-Tao,PENG Yong-Jin. Voltage Synchronous Triggering Scheme Clocked by Phase-Locked Loop[J]. Power Electronics, 2007, 41(1): 125-126 |
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| Authors: | LIU Zheng ZHAO Yan-Tao PENG Yong-Jin |
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| Affiliation: | Hunan University, Changsha 410082, China |
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| Abstract: | For keeping the strict phase relation between the thyristor triggering pulses and the voltage of the main circuit,this paper provide a synchronous triggering scheme which based on Complex Programmable Logic Device(CPLD) whose clock source is phase-lock loop.The scheme can eliminate the dissymmetry of 3-phase triggering pulse which caused by quantification,and simplify the programming of CPLD.The experimental results show that the scheme is credible and practical. |
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| Keywords: | thyristor trigger phase-lock loop |
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