| 8254的Verilog实现和FPGA验证 |
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| 引用本文： | 王亮,张盛兵,谭永亮,潘永峰.8254的Verilog实现和FPGA验证[J].电子测量技术,2008,31(1):150-152. |
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| 作者姓名： | 王亮 张盛兵 谭永亮 潘永峰 |
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| 作者单位： | 西北工业大学计算机科学与工程系,西安,710072 |
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| 基金项目： | 国家自然科学基金(60573107)，西安应用材料创新基金(XA-AM-200509) |
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| 摘 要： | 用verilog硬件描述语言实现了定时/计数器8254的RTL模型,该模型与标准8254功能时序完全相同,可作为一个IP核嵌入SOC系统。在此基础上,提出了一种FPGA单模块验证方法——ROM施加激励法,并在Altera Stratix EP1S80上予以实现,对上述8254IP核进行了全面的功能和时序验证。
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| 关 键 词： | IP Verilog FPGA验证 |
8254 implementation and verification on FPGA |
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| Wang Liang,Zhang Shengbing,Tan Yongliang,Pan Yongfeng.8254 implementation and verification on FPGA[J].Electronic Measurement Technology,2008,31(1):150-152. |
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| Authors: | Wang Liang Zhang Shengbing Tan Yongliang Pan Yongfeng |
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| Abstract: | This paper implements the RTL model of 8254 with Verilog HDL.The model is completely compatible with standard 8254,which can be integrated into SOC as an IP core.Based on this,this paper brings forward a method of verification for single module using FPGA.The method uses an extra ROM instance which store test vectors for verification.With this method,8254 is fully verified in both function and timing on Altera Straix EP1S80 FPGA. |
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| Keywords: | IP Verilog FPGA verification |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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