Parallel counter implementation |
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| Authors: | Robert F. Jones Jr. and Earl E. Swartzlander Jr. |
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| Affiliation: | (1) Advanced Micro Devices, Inc., 5204 E. Ben White Blvd., 78741 Austin, TX;(2) Department of Electrical and Computer Engineering, University of Texas at Austin, 78712 Austin, TX |
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| Abstract: | An (n, m) parallel counter is a circuit withn inputs that produces anm-bit binary count of the number of its inputs that are ONEs. This article reports on the design of large parallel counters with up to 1023 inputs. Design trade-offs are examined regarding the use of counter cells of size ranging from (3,2) to (31,5) as building blocks. |
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