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Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip |
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| Authors: | D Barros Júnior M Rodriguez-Irago M B Santos I C Teixeira F Vargas J P Teixeira |
| Affiliation: | (1) PUCRS, Porto Alegre, Brazil;(2) IST/INESC-ID, Lisboa, Portugal;(3) PUCRS, Porto Alegre, Brazil;(4) IST/INESC-ID, Lisboa, Portugal |
| Abstract: | |
| Keywords: | fault tolerance intermittent faults modeling and simulation digital SoC EMI/EMC standard compliance delay fault simulation power supply voltage transients |
| 本文献已被 SpringerLink 等数据库收录！ | |