一种新颖的用于RF-CMOS工艺片上层叠变压器的紧凑型模型

A novel compact model for on-chip stacked transformers is presented.The proposed model topology gives a clear distinction to the eddy current,resistive and capacitive losses of the primary and secondary coils in the substrate.A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided.The model is further verified by the excellent match between the measured and simulated S-parameters on the extracted parameters for a 1:1 stacked transformer manufactured in a commercial RF-CMOS technology.

A novel compact model for on-chip stacked transformers in RF-CMOS technology

A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S-parameters on the extracted parameters for a 1:1 stacked transformer manufactured in a commercial RF-CMOS technology.