A 0.7-2-GHz self-calibrated multiphase delay-locked loop

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-/spl mu/m CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree).