使用传输线理论的硅通孔电参数提取方法

针对三维集成电路中的关键技术硅通孔的电特性,使用传输线理论提取了其单位长度RL-GC参数。将硅通孔等效为传输线,利用HFSS仿真结果并结合传输线理论给出了具体的参数提取方法。计算结果表明,硅通孔单位长度RLGC 参数呈现较强的频变特性,当频率从1 MHz增加到20 GHz时,单位长度的电阻和导纳分别从0.45 mΩ/μm和2.5μS/μm增加到2.5 mΩ/μm和17μS/μm,而单位长度电感和电容分别从8.7 pH/μm和8.8 fF/μm减小至7.5 pH/μm和0.2 fF/μm。与传统的阻抗矩阵和导纳矩阵提取方法相比,该方法具有结果绝对收敛和适用频率高等诸多优点,可进一步应用于三维集成电路的仿真设计。

Through-silicon-via parasitics extraction based on transmission line theory

Through-Silicon-Via ( TSV ) is a key technology for three-dimentional integrated circuits ( 3 D ICs) . The parasitic RLGC parameters are extracted through transmission line theory( TLT) according to its characteristic. Firstly,the TSV is treated as a lossy transmission line. Then,the parasitic electrical parame-ters are extracted from the simulation results of TSV pair with HFSS and TLT. The computation results show that per unit RLGC parameters vary with the change of frequency. The resistance and admittance per unit length increases from 0 . 45 mΩ/μm and 2 . 5 μS/μm to 2 . 5 mΩ/μm and 17 μS/μm respectively when the frequency increases from 1 MHz to 20 GHz. Meanwhile,the inductance and capacitor per unit length deceases from 8. 7 pH/μm and 8. 8 fF/μm to 7. 5 pH/μm and 0. 2 fF/μm respectively. Compared with tradition methods,such as impedance matrix and admittance matrix,the proposed TLT method is fea-tured by absolute convergence and being more suitable for high frequency application. Moreover,the TLT method is further applicable to the design and analysis of 3D ICs through the full circuit simulation.