Dynamically shift-switched dataline redundancy suitable for DRAMmacro with wide data bus |
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| Authors: | Namekawa T. Miyano S. Fukuda R. Haga R. Wada O. Banba H. Takeda S. Suda K. Mimoto K. Yamaguchi S. Ohkubo T. Takato H. Numata K. |
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| Affiliation: | Microelectron. Eng. Lab., Toshiba Corp., Yokohama ; |
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| Abstract: | A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is presented. This redundancy reduces the area required for spare cells from 6 to 1.6% of the area required for normal cells and improves chip yield from 50 to 80%. In addition, it provides a high-speed data path. An embedded DRAM macro adopting the redundancy achieves 200-MHz operation and provides 51.2-Gbit/s bandwidth. It has been fabricated with 0.25-μm technology |
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