对AES算法硬件实现的面积优化的研究

本文从AES算法入手,对有效缩减面积的多类硬件实现方法设计进行了研究.这些方法主要有三类:对单独的层(layer)分别进行优化;将相邻的层组合在一起进行优化;将加解密的相关模块集成优化.最后,基于SMIC0.18CMOS工艺,提出了一种有效缩减面积的设计,在满足实用要求的情况下,该设计有效的减少了芯片的面积.

The Research on Area-efficient Advanced Encryption Standard(AES) Processor Designs

In this paper, we propose area-efficient Advanced Encryption Standard (AES) processor designs by applying some novel efficient area reduction solutions in AES encryption and decryption. The first category pay attention to the optimizations on separate modules, the second category is derived by combining adjacent transformations in each AES round into a new transformation. The last category is from the integrated transformations in the AES encryption and decryption process with shared common operations. Besides, we proposed an architecture which applies the proposed methods. Cell-based implementation results show that the designs can achieve am area reduction significantly compared with Synopsys optimization results.