Hazard simulation of sequential circuits |
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| Authors: | Kanji Hirabayashi |
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| Affiliation: | (1) Toshiba Corporation, Research and Development Center, 1, Komukai Toshibacho, Saiwaiku, 210 Kawasaki, Japan |
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| Abstract: | A 7-valued logic appropriate for hazard simulation of sequential circuits is investigated in this letter. The 5-valued system of Lin and Reddy is extended to discriminate transitions with and without hazard. We assume that hazards are damped in the feed-back loop of flip-flops, and introduce a kind of filter to assure it. The application to hazard checking is demonstrated for counter circuits. |
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| Keywords: | hazard checking logic simulation seven-valued logic |
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