| 基于EDK的高速数据收发嵌入式用户IP核设计 |
| |
| 引用本文： | 范晓星,席鹏飞,孟琪. 基于EDK的高速数据收发嵌入式用户IP核设计[J]. 电子科技, 2015, 28(2): 164 |
| |
| 作者姓名： | 范晓星 席鹏飞 孟琪 |
| |
| 作者单位： | (西安电子科技大学 电子信息攻防对抗与仿真技术教育部重点实验室,陕西 西安 710071) |
| |
| 摘 要： | 介绍了基于FPGA嵌入式系统的多通道高速数据收发模块的用户IP核设计。在Xilinx公司的ISE开发工具中,用FPGA器件中的硬核RocketIO及软核FIFO设计用户逻辑;使用嵌入式开发工具EDK封装成可在FPGA嵌入式系统中使用的用户自定义IP核,最后通过实际测试验证了该方法的实效性。
|
| 关 键 词： | FPGA EDK 嵌入式 IP核 NPI总线 RocketIO MPMC PLB总线 |
Design of High-speed Data Transceiver Embedded User IP Core Based on EDK |
| |
| FAN Xiaoxing,XI Pengfei,MENG Qi. Design of High-speed Data Transceiver Embedded User IP Core Based on EDK[J]. Electronic Science and Technology, 2015, 28(2): 164 |
| |
| Authors: | FAN Xiaoxing XI Pengfei MENG Qi |
| |
| Affiliation: | (Ministry of Education Key Laboratory of Electronic Information Countermeasure and Simulation Technology Ministry of Education,Xidian University,Xi'an 710071,China) |
| |
| Abstract: | This paper introduces the user IP core design of multi-channel high-speed data transceiver module FPGA-based embedded systems.Of the Xilinx's ISE development tools,FPGA devices hardcore and soft-core FIFO RocketIO is used to design the user logic.The custom FPGA IP core used in embedded systems is packed using the embedded development tools of EDK.The effectiveness of the method is verified by actual test. |
| |
| Keywords: | FPGA EDK embedded IP core NPI bus RocketIO MPMC PLB bus, |
| 本文献已被 万方数据 等数据库收录！ |
| 点击此处可从《电子科技》浏览原始摘要信息 |
|
点击此处可从《电子科技》下载全文 |
