Fault model for sub-micron CMOS ULSI circuits reliability assessment

A new fault model, based on the general Percolation theory applied to long-channel CMOS VLSI circuits, has been recently introduced. It was shown that a reliability risk appears only when process-related defects create a pattern independent current path in standby mode. An acceptable reliability risk defines pass/fail criteria. A screening technique, based on this model, presents a strong correlation between rejected devices and Early Failure Rate.In this paper, the general Percolation approach was applied to short-channel CMOS VLSI circuits. Unlike long-channel CMOS VLSI, defect-free short-channel CMOS VLSI circuits inherently have a pattern-independent standby current. It results from a short-channel MOSFET current in the off state. In this case, the defect-related component of this current might be released only by means of a multi parameter fail criterion. Experimental results that confirm this conclusion are presented and discussed. The Reliability Risk assessment technique employing this model shows a strong correlation between rejected devices and long term reliability for 32-bit 0.35 μM CMOS microprocessors.