Improving bulk FinFET DC performance in comparison to SOI FinFET |
| |
Authors: | Mirko Poljak, Vladimir Jovanovi ,Tomislav Suligoj |
| |
Affiliation: | aDepartment of Electronics, Microelectronics, Computer and Intelligent Systems, Faculty of Electrical Engineering and Computing, University of Zagreb, Unska 3, HR-10000 Zagreb, Croatia |
| |
Abstract: | The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have shown that bulk FinFET with source/drain-to-body (S/D) junctions shallower than gate-bottom has equal or better subthreshold performance than SOI FinFET. By reducing S/D junction depth, fin width scaling for suppression of short-channel-effects (SCEs) can be relaxed. On-state performance has also been examined and drain current difference between the SOI and bulk FinFET at higher body doping levels has been explained by investigating enhanced conduction in silicon-oxide interface corners. By keeping the body doping low and junctions shallower than the gate-bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost. |
| |
Keywords: | Body-tied Corner effect Double-gate MOSFET FinFET Silicon-on-insulator (SOI) Short-channel-effect (SCE) |
本文献已被 ScienceDirect 等数据库收录! |
|