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The hierarchical logic schematic capture |
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| Affiliation: | 1. Department of Electrical and Computer Engineering, The University of Texas at Dallas, USA;2. Department of Electronic and Information Engineering, The Hong Kong Polytechnic University, HK SAR, China;3. Centro del Electrónica Industrial, Universidad Politécnica de Madrid, Spain |
| Abstract: | A graphic package called Hierarchical Logic Schematic Capture (CAPTURE) has been developed as a design aid for fast turnaround and high complexity LSI/VLSI designs. The data structure to represent the complete model of a hierarchical logic schematic and to handle automatic node assignment is discussed. Conclusions are drawn with the case study of using the package to design a given circuit. |
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