Oscillation Ring Delay Test for High Performance Microprocessors |
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| Authors: | Wen Ching Wu Chung Len Lee Ming Shae Wu Jwu E Chen Magdy S Abadir |
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| Affiliation: | (1) Department of Electronics Engineering, National Chiao Tung University, Hsin Chu, Taiwan, ROC;(2) Department of Electronics Engineering, National Chiao Tung University, Hsin Chu, Taiwan, ROC;(3) Department of Electrical Engineering, Chung Hwa University, Hsin Chu, Taiwan, ROC;(4) Motorola Inc., Somerset Design Center, Austin, TX, USA |
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| Abstract: | This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors. |
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| Keywords: | oscillation ring testing delay fault testing sensitized path gate delay fault robust path dealy fault stuck at fault hazard-free path delay fault multiple reconvergent fanout flunk lines |
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