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| 基于FPGA与DDR2 SDRAM的大容量异步FIFO缓存设计 | |
| 引用本文： | 庾志衡,叶俊明,邓迪文.基于FPGA与DDR2 SDRAM的大容量异步FIFO缓存设计[J].微型机与应用,2011,30(4):34-36,40. |
| 作者姓名： | 庾志衡 叶俊明 邓迪文 |
| 作者单位： | 1. 桂林电子科技大学,电子工程与自动化学院,广西,桂林,541004 2. 桂林电子科技大学,职业技术学院电子信息工程系,广西,北海,536000 3. 深圳市怡化电脑有限公司,广东,深圳,518026 |
| 基金项目： | 广西教育厅科研基金资助项目 |
| 摘 要： | 为了满足高速实时数据采集系统对所采集海量数据进行缓存的要求,通过研究FIFO的基本工作原理,利用FPGA和DDR2 SDRAM设计了一种高速大容量异步FIFO。使用Xilinx提供的存储器接口生成器(MIG)实现FPGA与DDR2的存储器接口,并结合片上FIFO和相应的控制模块完成FIFO的基本框架结构。详细介绍了各个组成模块的功能和原理,并设计了专门的测试模块。 |
| 关 键 词： | 高速大容量异步FIFO MIG FPGA DDR2 SDRAM |
A design of high speed and deep asynchronous FIFO based on FPGA and DDR2 SDRAM |
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| Yu Zhiheng,Ye Junming,Deng Diwen.A design of high speed and deep asynchronous FIFO based on FPGA and DDR2 SDRAM[J].Microcomputer & its Applications,2011,30(4):34-36,40. | |
| Authors: | Yu Zhiheng Ye Junming Deng Diwen |
| Affiliation: | Yu Zhiheng1,Ye Junming2,Deng Diwen3(1.School of Electronic Engineering and Automation,Guilin University of Electronic Technology,Guilin 541004,China,2.Department of Electronic Information Engineering,Professional Technical Institute,Beihai 536000,3.Shenzhen Yihua Computer Ltd,Shenzhen 518026,China) |
| Abstract: | To satisfy the request of buffering the mass data in the high speed real-time data gathering system,a high speed and deep asynchronous FIFO based on FPGA and DDR2 SDRAM is designed after researching FIFO's principle.The interface between FPGA and DDR2 SDRAM is designed with memory interface generator(MIG) supplied by Xilinx,combined with two FIFO and other control models form the FIFO's fabric.The models' function and princples were intriduced detailedly,in addition,a special test module is designed to vali... |
| Keywords: | MIG FPGA DDR2 SDRAM |
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