Microarchitectural dl/dt control |
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Authors: | Grochowski E Ayers D Tiwari V |
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Affiliation: | Univ. of California, Berkeley, CA, USA; |
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Abstract: | This article takes a high level of the power-grid noise problem as it relates to the microarchitectural definition of an IC. Through a set of simulations, the authors relate the noise problem to the details of the circuit and clocking implementation giving insight into the possible method to reduce such noise. |
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