一种适用于JPEG2000的高速MQ编码器的VLSI实现

MQ编码器对于无损的数据压缩是一种非常有效的方法 ,它已被 JPEG2 0 0 0标准所采用。但该编码算法复杂度高 ,执行速度慢。文中提出了一种基于动态流水的高性能 MQ编码器的 VLSI结构。为了获得高速处理能力 ,首先分析了 JPEG2 0 0 0标准中 MQ编码算法的软件流程 ,并对其进行了相应的修改以适应硬件实现 ,然后采用了“动态流水”技术 ,可以根据变化的运算量来实时地安排流水操作。本 MQ编码器结构经 Xilinx FPGA实现 ,处理速度可达约 0 .6 2 5bit/ cycle( 32 .83Mbit/ sec)

A VLSI Implementation of a High-speed MQ-coder for JPEG2000

MQ-coder is an ef ficient technique for lossless data comp ression,which has been adopted in JPEG20 00 standard.But the coding algorithm is very complex and performs slowly.In this paper,a dynamic pipelined VLSI architec ture with high performance for MQ-coder is presented.To achieve a high throughpu t,we first analyze the software flow of MQ-coding algorithm in JPEG2000 standard ,and modified some operations to suit ha rdware implementation.Then the dynamic p ipelining technique is adopted to pipeli ne the coding process with variant laten cies effectively.The whole digital syste m is implemented with Xilinx FPGA,and th e execution speed achieves almost 0.625 bit/cycle(32.83 Mbit/sec).