Low-power high-sensitivity spike detectors for implantable VLSI neural recording microsystems

A spike detector has become a necessity of a contemporary multichannel neural recording microsystem for data-compression. This paper proposes two spike detection algorithms, frequency-enhanced nonlinear energy operator (fNEO) and energy-of-derivative (ED), to solve the sensitivity degradation suffered by the conventional nonlinear energy operator (NEO) at the presence of large-amplitude baseline interferences. The efficiency of NEO, fNEO and ED algorithms are evaluated with Simulink programs firstly and then implemented into three low-power spike detectors with a standard 0.13- (mu m) CMOS process. To achieve a low-power design, subthreshold CMOS analog multipliers, derivatives and adders are developed to work with a low supply voltage, 0.5 V. The power dissipation of the proposed fNEO spike detector and ED spike detector are only 258.7 and 129.4 nW, respectively. The quantitative investigation shown in the paper indicates that both fNEO and ED spike detectors achieves superior performance than the conventional NEO spike detector. Considering its lowest power dissipation, the ED spike detector is selected for our application. Further statistical evaluations based on the true positive and false positive detection rate proves that the ED spike detectors achieves higher detection rate than that of the conventional NEO spike detector but dissipates 48 % less power.