Magnetization dynamics, throughput and energy dissipation in a universal multiferroic nanomagnetic logic gate with fan-in and fan-out

The switching dynamics of a multiferroic nanomagnetic NAND gate with fan-in/fan-out is simulated by solving the Landau-Lifshitz-Gilbert (LLG) equation while neglecting thermal fluctuation effects. The gate and logic wires are implemented with dipole-coupled two-phase (magnetostrictive/piezoelectric) multiferroic elements that are clocked with electrostatic potentials of ~50 mV applied to the piezoelectric layer generating 10.1 MPa stress in the magnetostrictive layers for switching. We show that a pipeline bit throughput rate of ~0.5 GHz is achievable with proper magnet layout and sinusoidal four-phase clocking. The gate operation is completed in 2 ns with a latency of 4 ns. The total (internal + external) energy dissipated for a single gate operation at this throughput rate is found to be only ~500 kT in the gate and ~1250 kT in the 12-magnet array comprising two input and two output wires for fan-in and fan-out. This makes it respectively three and five orders of magnitude more energy-efficient than complementary-metal-oxide-semiconductor-transistor (CMOS)-based and spin-transfer-torque-driven nanomagnet-based NAND gates. Finally, we show that the dissipation in the external clocking circuit can always be reduced asymptotically to zero using increasingly slow adiabatic clocking, such as by designing the RC time constant to be three orders of magnitude smaller than the clocking period. However, the internal dissipation in the device must remain and cannot be eliminated if we want to perform fault-tolerant classical computing.