| 采用分布式算法的高速FIR滤波器ASIC设计 |
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| 引用本文： | 陈亦欧,李广军.采用分布式算法的高速FIR滤波器ASIC设计[J].微电子学,2007,37(1):144-146. |
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| 作者姓名： | 陈亦欧 李广军 |
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| 作者单位： | 电子科技大学,通信与信息工程学院,四川,成都,610054 |
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| 摘 要： | 对DA算法的FIR滤波器和传统乘加结构FIR滤波器的性能进行了比较,介绍了改进DA算法的原理;对分别采用FPGA和芯片实现的DA算法高速FIR滤波器的性能指标进行了比较;介绍了ASIC芯片设计时存储器的可测性设计方法,以及存储器对布局布线策略的影响。最后,给出了版图形式的设计结果及电路验证信号波形。
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| 关 键 词： | DA算法 FIR滤波器 专用集成电路 可测性设计 |
| 文章编号： | 1004-3365（2007）01-0144-03 |
| 修稿时间： | 2006-05-172006-10-09 |
Design of a High Speed FIR Filter ASIC Using Distributed Arithmetic |
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| CHEN Yi-ou,LI Guang-jun.Design of a High Speed FIR Filter ASIC Using Distributed Arithmetic[J].Microelectronics,2007,37(1):144-146. |
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| Authors: | CHEN Yi-ou LI Guang-jun |
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| Affiliation: | School of Commun. and Inform. Engineer., Univ, of Elec. Sci. and Technol, of China, Chengdu, Sichuan 610054, P. R. China |
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| Abstract: | Performances of FIR filters using MAC architecture and distributed arithmetic(DA) are compared,and the principle of distributed arithmetic is described.Performances of DA based FIR filters implemented in FPGA and IC chip are also compared.The design for testability of memory in ASIC design is dealt with and the influence of memory on placement and routing in IC design is analyzed.Finally,the layout design and FPGA verification of a DDC chip using DA based FIR filter is provided. |
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| Keywords: | Distributed arithmetic FIR filter ASIC Design for testability |
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