A 400 K-transistor CMOS sea-of-gates array with continuous track allocation |
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| Authors: | Okabe M. Okuno Y. Arakawa T. Tomioka I. Ohno T. Noda T. Hatanaka M. Kuramitsu Y. |
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| Affiliation: | LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Hyogo, Japan; |
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| Abstract: | A 0.8- mu m CMOS sea-of-gates (SOG) array with first-level wiring channels perpendicular to transistor rows and 40 0K transistors is integrated on a 6*7-mm/sup 2/ chip. Implementation of a 64-bit multiplier shows 60-percent gate utilization and density of 1410 G/mm/sup 2/. The wiring length of the multiplier is 70 percent of that in a conventional SOG.<> |
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