The impact of device scaling and power supply change on CMOS gateperformance

Based a new empirical mobility model that is solely dependent on V _gs, V_t, and T_ox and a corresponding saturation drain current (I_dsat) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the T_ox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V_dd (for low power applications) if V_t can be lowered