| 边界扫描在PCB缺陷测试中的应用 |
| |
| 引用本文： | 刘家欣,肖大雏,王彬如. 边界扫描在PCB缺陷测试中的应用[J]. 计算机测量与控制, 2004, 12(5): 401-404 |
| |
| 作者姓名： | 刘家欣 肖大雏 王彬如 |
| |
| 作者单位： | 武汉大学,自动化系,湖北,武汉,430072;武汉大学,自动化系,湖北,武汉,430072;武汉大学,自动化系,湖北,武汉,430072 |
| |
| 摘 要： | 硬件系统的规模越来越大，复杂程度越来越高，对其进行测试也越来越困难，边界扫描技术很好地解决了传统测试的不足。通过分析边界扫描技术在PCB缺陷测试中的应用原理，提出了一种可以广泛应用、低廉高效的边界扫描测试方法-PPT，实现对系统级、PCB级和芯片级集成电路进行边界扫描测试的功能。
|
| 关 键 词： | JTAG BST 针床 ICT BGA |
| 文章编号： | 1671-4598(2004)05-0401-02 |
| 修稿时间： | 2003-09-10 |
Application of Boundary Scan Test Technique in PCB Failure Test |
| |
| Liu Jiaxin,Xiao Dachu,Wang Bingru. Application of Boundary Scan Test Technique in PCB Failure Test[J]. Computer Measurement & Control, 2004, 12(5): 401-404 |
| |
| Authors: | Liu Jiaxin Xiao Dachu Wang Bingru |
| |
| Abstract: | As the scale and complexity of hardware systems increase quickly , it is now a more difficult task to test them .The BST technique can well make up the shortcoming of traditional test techniques. In this article, the basic concepts of Boundary Scan Test Technology applied in PCB connection test is introduced firstly .Then an applied widely,low cost and effective BST implement -PPT(Parallel Port Test) is presented.The system can accomplish boundary scan test for system, PCB, chip level integrated circuit. |
| |
| Keywords: | JTAG BST bed of nails ICT BGA |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
