A very-high output impedance charge pump for low-voltage low-power PLLs |
| |
Authors: | L.-F. Tanguay M. Sawan Y. Savaria |
| |
Affiliation: | Electrical Engineering Department, Ecole Polytechnique de Montreal, Montreal, QC, Canada H3C 3A7 |
| |
Abstract: | This article presents the design of a high output compliance, very-high output impedance single-ended charge pump implemented using a new low-voltage current mirror. The output current is sampled and a feedback loop forces it to be equal to the desired reference current. This results in a very-high output impedance over a very wide output voltage range, accurate Up/Down current matching, and low transient glitches. The proposed charge pump was implemented using STMicroelectronics 1-V 90-nm CMOS process. Simulations using Spectre show that the Up/Down output currents remain constant and matched within 1% over a charge pump output voltage ranging from 119 to 873 mV. Monte Carlo process variations and mismatch simulations indicate that the 1-σ standard deviation between the Up and Down current components is , or 6.8% of the nominal charge pump current at either end of the output voltage range. |
| |
Keywords: | Charge pumps Current mirrors Phase-locked loops (PLLs) Low-voltage analog CMOS design Biomedical implants |
本文献已被 ScienceDirect 等数据库收录! |