Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron

This paper presents a performance comparison of a carbon nanotube-based field effect (CNFET)- and CMOS-based 6T SRAM cell at the 32 nm technology node. HSPICE simulations, carried out using Berkeley predictive technology model (BPTM), show that for a cell ratio and pull-up ratio of 1, CNFET-based 6T SRAM cell provides an improvement of 21% in read static noise margin (SNM) at VDD=0.4 V. The speed of CNFET cell is 1.84× that of CMOS cell. The standby leakage of CNFET cell is 84% less than CMOS cell. The process parameter variation results in 1.2% change in the read SNM of CNFET cell as compared with a wide variation of around 10.6% in CMOS cell.