Advanced model and analysis of series resistance for CMOS scalinginto nanometer regime. I. Theoretical derivation |
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Authors: | Seong-Dong Kim Cheol-Min Park Woo JCS |
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Affiliation: | Dept. of Electr. Eng., California Univ., Los Angeles, CA; |
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Abstract: | An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by division into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance, considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high-κ dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization |
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