A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation |
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| Authors: | Y Li SM Sze T-S Chao |
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| Affiliation: | (1) National Nano Device Laboratories, Hsinchu, Taiwan, TW;(2) Microelectronics and Information Systems Research Center, National Chiao Tung University, Hsinchu, Taiwan, TW;(3) Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, TW;(4) Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan, TW |
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| Abstract: | We present a new parallel semiconductor device simulation using the dynamic load balancing approach. This semiconductor device
simulation based on the adaptive finite volume method with a posteriori error estimation has been developed and successfully implemented on a 16-PC Linux cluster with a message passing interface
library. A constructive monotone iterative technique is also applied for solution of the system of nonlinear algebraic equations.
Two different parallel versions of the algorithm to perform a complete device simulation are proposed. The first is a dynamic
parallel domain decomposition approach, and the second is a parallel current-voltage characteristic points simulation. This
implementation shows that a well-designed load balancing simulation can significantly reduce the execution time up to an order
of magnitude. Compared with the measured data, numerical results on various submicron VLSI devices are presented, to show
the accuracy and efficiency of the method. |
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| Keywords: | : DTMOS Dynamic domain decomposition Linux cluster Load balancing MOSFET Parallel I– V points calculation VLSI device simulation |
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