一种应用于低噪声PLL的RF-VCO设计

在PLL电路设计中,压控振荡器设计是电路的关键模块,按类型又主要分为LC震荡器和环形振荡器两种,其性能直接决定了相位噪声、频率稳定度及覆盖范围。文章介绍了一款1.8 GHz的基于交叉耦合对LC结构的低噪声CMOS压控振荡器的设计,并对调谐范围、相位噪声以及电路起振条件等做了分析讨论。该设计采用0.18μm 6层金属CMOS工艺制造,模块面积为0.3 mm2,电路经过Cadence SpectreRF仿真,VCO的输出范围为1 594~2 023 MHz,中心频率1.8 GHz输出时相位噪声为-118 dBc/Hz@600 kHz,1.9 GHz输出时相位噪声为-121 dBc/Hz@600 kHz。结果表明该VCO设计达到了较宽的频率覆盖范围和较低的相位噪声,可以满足低噪声PLL的设计要求。

Design of a RF-VCO for Low-Phase-Noise PLL

The VCO circuit is the key parts in the PLL, include LCVCO and ring VCO, its character determines the phase noise, frequency stability and range of PLL. A 1.8 GHz low-phase-noise CMOS VCO was designed, this design is base on cross-coupled LC oscillators, and the VCO was implemented in a 0.18 pm CMOS process with six standard metal layers. The layout area is 0.3 mm2, and the simulation results in Cadence SpectreRF shows the oscillation frequency can be varied in the range 1594 MHz to 2 023 MHz, and the phase noise of -118 dBc/Hz@600 kHz offset at the frequency of 1.8 GHz, -121 dBc/Hz@600 kHz offset at the frequency of 1.9 GHz, it can be used in low-phase-noise PLL.