Dynamic positive feedback source-coupled logic (D-PFSCL) |
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Authors: | Kirti Gupta Maneesha Gupta |
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Affiliation: | 1. Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India;2. Department of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, Delhi, India |
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Abstract: | This paper presents dynamic positive feedback source-coupled logic (D-PFSCL) style which is derived from positive feedback source-coupled logic (PFSCL). The proposed logic style uses dynamic current source in contrast to constant current source of PFSCL to attain lower power consumption. Two techniques for D-PFSCL style-based multistage applications are suggested. Several D-PFSCL gates are simulated and compared with the respective PFSCL counterparts through SPICE simulations by using Taiwan semiconductor manufacturing company 0.18 µm CMOS technology parameters. A maximum power reduction of 84% is achieved for D-PFSCL gates. The effect of process variation on the power consumption of the D-PFSCL gates shows a maximum variation factor of 1.5 between the best and the worst cases. |
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Keywords: | Single-ended SCL PFSCL low power dynamic circuits positive feedback |
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