Digital background calibration of charge pump based pipelined ADC |
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Authors: | Anil Singh Alpana Agarwal |
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Affiliation: | Electronics and Communication Engineering Department, Thapar University, Patiala, India |
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Abstract: | In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power. |
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Keywords: | Charge pump pipelined ADC digital background calibration low power linear gain error |
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