Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications

In this paper, we report the TCAD based simulation of a new double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends. The proposed structure not only improves the ON to OFF drain current ratio (by \({\sim }\)900 %), subthreshold swing characteristics (by \({\sim }\)12 %) and Drain Induced Barrier Lowering (DIBL) (by \({\sim }\)56 %) over the conventional DG-JLFETs (i.e. without DPs), but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs. Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs with improved performance.