| 基于FPGA的高效内积运算IP模块设计 |
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| 引用本文： | 熊承义,田金文,柳健. 基于FPGA的高效内积运算IP模块设计[J]. 微电子学, 2004, 34(1): 94-96 |
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| 作者姓名： | 熊承义 田金文 柳健 |
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| 作者单位： | 华中科技大学,图像识别与人工智能研究所,图像信息处理与智能控制教育部重点实验室,湖北,武汉,430074 |
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| 摘 要： | 基于现场可编程门阵列器件，采用分布式运算算法，实现了一种面积有效内积运算IP核的设计。充分考虑计算的特点，提出了一种采用对输入进行编码实现存储器减少的技术和高效的实现结构，有效地减少了所用查找表的容量，极大地减少了系统实现的硬件资源需求。编写了相应的Veriloz HDL模型，并进行了行为仿真和综合。
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| 关 键 词： | FPGA 内积运算IP模块 设计 现场可编程门阵列器件 分布式运算算法 查找表 IP核 |
| 文章编号： | 1004-3365(2004)01-0094-03 |
Implementation of an FPGA-Based IP Core for High-Efficiency Inner-Product Computation |
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| XIONG Cheng-yi,TIAN Jin-wen,LIU Jian and Intelligent Control. Implementation of an FPGA-Based IP Core for High-Efficiency Inner-Product Computation[J]. Microelectronics, 2004, 34(1): 94-96 |
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| Authors: | XIONG Cheng-yi TIAN Jin-wen LIU Jian Intelligent Control |
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| Affiliation: | XIONG Cheng-yi,TIAN Jin-wen,LIU Jian and Intelligent Control,Institute of Pattern Recognition & Artificial Intelligence,Huazhong University of Science & Technology,Wuhan,Hubei 430074,P. R. China) |
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| Abstract: | An IP core based-on FPGA for high-efficiency inner-product operation is implemented,in which a distributed arithmetic algorithm was introduced to compute inner-product. The required amount of ROM used for look-up-table is decreased significantly by using two memory reduction techniques,thus saving the hardware resources. Verilog HDL for the IP core is described,and the functional simulation and synthesis are carried out under Xilinx ISE4.1. |
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| Keywords: | Inner-product FPGA Distributed arithmetic algorithm Look-up-table IP core |
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