| 12位60MS/s采样保持电路的设计 |
| |
| 引用本文： | 刘睿强,景新幸,王晓晖.12位60MS/s采样保持电路的设计[J].桂林电子科技大学学报,2007,27(1):14-18. |
| |
| 作者姓名： | 刘睿强 景新幸 王晓晖 |
| |
| 作者单位： | 桂林电子科技大学,信息与通信学院ASIC研究室,广西,桂林,541004 |
| |
| 摘 要： | 通过增益提升电路,使用于高速高分辨率ADC中的CMOS全差分采样保持电路,能达到高增益高带宽.利用电容下级板采样技术和自举开关消除电荷注入,以全差分结构抑制噪声来提高线性度,使采样精度达到了0.012%.经过Cadence软件Hspice平台仿真,在3.3V电源电压下,用TSMC0.20umCMOS工艺模型,在驱动2PF负载时,直流增益可达112DB,相位裕度为69.7度,单位增益带宽为547.2MHz,压摆率463V/us,功耗19.1 mW.
|
| 关 键 词： | 采样保持 CMOS运算放大器 增益提升 自举开关 |
| 文章编号： | 1673-808X（2007）01-0014-05 |
| 修稿时间： | 2006-11-11 |
Designing of a 12-bit 60MS/s sample-and-hold circuit |
| |
| LIU Rui-qiang,JING Xin-xing,WANG Xiao-hui.Designing of a 12-bit 60MS/s sample-and-hold circuit[J].Journal of Guilin Institute of Electronic Technology,2007,27(1):14-18. |
| |
| Authors: | LIU Rui-qiang JING Xin-xing WANG Xiao-hui |
| |
| Affiliation: | School of Information and Communication Engineering, Guilin University of Electronic Technology, Guilin 541004, China |
| |
| Abstract: | This paper first discusses using a gain-boosted circuit to design a CMOS fully differential sample-and-hold circuit which is used in the high-speed and high-resolving ADC.The design objective of high dc gain and GBW is obtained.The charge injection is removed through the capacitance subordinate sample technique and boosted switch and the linearity and noise suppression are increased through the fully-differential structure.3.3 V power supply and TSMC 0.35um CMOS process technology are used to achieve the dc open-loop gain of 112 dB with 547.2MHz unity gain bandwidth,65 phase margin,463V/us slew rate and 19.1 mW power consumption. |
| |
| Keywords: | sample-and-hold CMOS amplifier gain-boosted boosted-switch |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
