Speed superiority of scaled double-gate CMOS |
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| Authors: | Fossum JG Lixin Ge Meng-Hsueh Chiang |
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| Affiliation: | Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL; |
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| Abstract: | Unloaded ring-oscillator simulations, performed with a generic process/physics-based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (VDD), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low VDD < ~1 V |
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