| OFDM基带系统接收器中高性能Viterbi译码器的FPGA实现 |
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| 引用本文： | 吴军,钟东波.OFDM基带系统接收器中高性能Viterbi译码器的FPGA实现[J].南方冶金学院学报,2011(3). |
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| 作者姓名： | 吴军 钟东波 |
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| 作者单位： | 江西理工大学信息工程学院; |
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| 摘 要： | 提出了一种应用于OFDM基带系统的高速Viterbi译码器的新结构,该译码器采用全并行结构以提高速度,采用矢量差的1范数代替欧氏距离作为软判决译码距离以减小硬件开销,以一种改进的归一化管理高效的解决了PMU单元的数据溢出问题,采用一种分块循环回溯算法以减少延时,并用Verilog语言具体实现.实验表明在该译码器以较少的资源实现了较快的速度,完全满足IEEE802.11a的协议标准,具有较高的实用价值.
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| 关 键 词： | FPGA 软判决 加比选单元 归一化处理 回溯算法 |
FPGA Implementation of a High-performance Viterbi Decoder in OFDM Baseband System |
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| WU Jun,ZHONG Dong-bo.FPGA Implementation of a High-performance Viterbi Decoder in OFDM Baseband System[J].Journal of Southern Institute of Metallurgy,2011(3). |
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| Authors: | WU Jun ZHONG Dong-bo |
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| Affiliation: | WU Jun,ZHONG Dong-bo(Faculty of Information Engineering,Jiangxi University of Science and Technology,Ganzhou 34100,China) |
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| Abstract: | This paper presents one new structure of high-performance Viterbi decoder applied in OFDM baseband system.The decoder uses full-parallel structure to improve speed,adopts 1_norm to replace Euclidean distance as soft decision distance to save hardware cost,employs a modified method of path metric normalization efficiently to solve the overflow of PMU,and applies a blocked cyclic memory trace-back scheme to reducing the delay of decoding.The decoder is designed in Verilog language.Simulations show that the mo... |
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| Keywords: | FPGA soft decision ACS unit path metric normalization trace-back algorithm |
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