| 基于FPGA的高速RS编码器的设计与实现 |
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| 引用本文： | 朱红,佟首峰,王奇涛. 基于FPGA的高速RS编码器的设计与实现[J]. 长春光学精密机械学院学报, 2013, 0(3): 23-25 |
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| 作者姓名： | 朱红 佟首峰 王奇涛 |
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| 作者单位： | 长春理工大学空地激光通信技术国防重点学科实验室,长春130022 |
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| 摘 要： | 本文主要研究RS时域编码器。首先分析了有限域下的RS码编码理论,并侧重于实现常系数并行乘法器。文中使用Verilog HDL语言的RS（255,239）编码器的设计方法,并搭建了验证平台,使用QuartusII验证功能和时序的正确性。最后,使用Modelsim仿真出结果,与Matlab仿真计算的结果一致。结果表明,编码器性能良好,与现有的设计相比,速度快和占用的硬件资源少。
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| 关 键 词： | 现场可编程门阵列 Reed-Solomon码 |
Design and Simulation of High Speed Reed-Solomon Encoder Based on FPGA |
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| ZHU Hong,TONG Shoufeng,WANG Qitao. Design and Simulation of High Speed Reed-Solomon Encoder Based on FPGA[J]. Journal of Changchun Institute of Optics and Fine Mechanics, 2013, 0(3): 23-25 |
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| Authors: | ZHU Hong TONG Shoufeng WANG Qitao |
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| Affiliation: | (National Defense Key Laboratory of Space to Ground Changchun University of Science and Technology Laser Communication Technique,Changchun 130022) |
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| Abstract: | Time-domain RS encoder is researched in this paper.The RS encoding theory in finite fields is analyzed,which is focused on realizing the parallel multiplier with constant coefficients.The design of the Verilog HDL language of RS（255,239）encoder is used.A verification platform is set up,and the circuit function and time sequence is verified using Quartus II.Modelsim simulation results are consistent with those of Matlab simulation.Results show that compared with existing design the encoder has better performance,such as higher speed and less hardware occupancy. |
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| Keywords: | field-programmable gate array reed-solomon code |
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